1. Field of the Invention
The present invention relates generally to software for reconfigurable computers, and more particularly to a compiling system and method for generating executable files for use by a partially reconfigurable processing unit having a dynamically reconfigurable portion and a non-reconfigurable portion.
2. Description of Background Art
Reconfigurable Computing
Related Application Ser. No. 08/423,560, entitled "System and Method for Scalable, Parallel, Dynamically Reconfigurable Computing," describes a software-programmed reconfigurable computing architecture employing field-programmable gate arrays (FPGAs). The architecture is scalable, flexible, and fully reconfigurable. During execution of instructions, the reconfigurable processor executes a number of reconfiguration directives, which instruct the processor to dynamically reconfigure its hardware organization to implement a specified instruction set architecture (ISA). An ISA is a primitive set of instructions that can be used to program a computer.
Related Application Ser. No. 08/827,619, entitled "Compiling System and Method for Reconfigurable Computing," describes a compiler for compiling source code written in a high-level language like C or Pascal into executable files for use in a fully reconfigurable processing unit. Moreover, it describes (1) a source-level declarative specification for selection of the reconfigurable architecture, (2) a multi-ISA code generator, (3) a technique for preserving the thread of control during hardware reconfiguration, and (4) a method for linking FPGA bitstreams into a separate section of the executable.
Partially Reconfigurable Computing
Recently, proposals have been made for a partially reconfigurable computing system including a standard microprocessor having some dynamically reconfigurable logic resources. These resources are used to implement special instructions that speed execution of particular programs. One such approach is disclosed by R. Razdan and M. D. Smith in "A High-Performance Microarchitecture with Hardware-Programmable Functional Units," Proceedings of the Twenty-Seventh Annual Microprogramming Workshop, IEEE Computer Society Press, 1994. The system includes a central processing unit (CPU) with a portion of the silicon die used to implement an FPGA. The CPU has a fixed data path to which the FPGA is connected.
Radzan also discloses a software environment for programming the hybrid FPGA/CPU processing unit. Specifically, an assembler is disclosed that accepts, as input, an assembly language program and outputs a new assembly language program in which particular sequences of instructions are automatically combined into single new assembly language instructions to be executed by the reconfigurable portion of the processor. Thus, Radzan automatically creates new ISAs at the time of assembly.
The software environment of Radzan, however, has a number of disadvantages. For example, the automatic ISA generation feature is limited to a narrow range of applications. No efficient method for automatically generating ISAs is demonstrated. Indeed, because such generation is an NP-hard problem, an efficient algorithm may not be possible. Additionally, because ISA generation is automatic, the programmer has only a coarse control over the code generated. Thus, the resulting code is likely to be less efficient than comparable code written by a programmer. Finally, the automatic ISA generation feature requires a highly complex assembler, which is more susceptible to unanticipated problems. What is needed, then, is an efficient compiler for compiling high-level source code into executable files for use by a partially reconfigurable processing unit having a dynamically reconfigurable portion and a non-reconfigurable portion.
Another hybrid sytem known as "Garp" is disclosed by John R. Hauser and John Wawrzynek in "Garp: A MIPS Processor with a Reconfigurable Coprocessor," IEEE Symposium on FPGAs for Custom Computing Machines, IEEE Computer Society Press, 1997. Garp includes a conventional MIPS processor and an FPGA slave computational unit located on the same die as the processor. Garp is designed to fit into an ordinary processing environment--one that includes structured programs, libraries, context switches, virtual memory, and multiple users. Moreover, in Garp, the main thread of control is managed by the non-reconfigurable MIPS processor, although for certain loops or subroutines, the program will switch temporarily to the reconfigurable FPGA to obtain an increase in execution speed.
Garp also provides software tools for writing programs that take advantage of the hybrid architecture. Specifically, it provides a configurator module for accepting a human-readable description of an FPGA configuration and producing therefrom a bitstream that can be hosted by the FPGA. Once created, the bitstream may be linked into an ordinary C program. However, like Radzan's system, the Garp compiler does not compile high-level language statements into assembly code for execution by the reconfigurable portion of the processor.
In addition, the Garp software environment has a number of other drawbacks. For example, since the FPGA configuration can only be invoked using a set of new Garp-specific instructions that are unknown to a standard compiler, the programmer must expressly provide assembly code to interface with to the FPGA. In particular, as presently disclosed, there is no means for automatically generating assembly code to load a configuration, perform register allocation, execute the configuration, and read a return value from the FPGA. Moreover, Garp's software environment has no means for determining the configuration currently in context within the FPGA. The compiler cannot, therefore, selectively generate code to reconfigure the FPGA depending on whether the target configuration is already loaded. Finally, as disclosed, the Garp programming environment expects that bitstreams are defined as character arrays in C, which are loaded by the linker into a standard data segment. This approach, however, does not provide any control over how the bitstream will be aligned in memory. A standard linker might, for example, load the bitstream at a byte rather than a word boundary, resulting in a misaligned bitstream. Many FPGAs will not function unless the bitstream is properly aligned within a multi-byte word.
What is needed, then, is a system and method for programming a partially reconfigurable processing unit such as the Garp processor using a high-level language without having to resort to assembly language in order to interface with the reconfigurable portion of the processor. Additionally, what is needed is a source-level declarative specification for a Garp program that can be used by a compiler to generate assembly code. Moreover, what is needed is a compiler that can selectively provide assembly code to reconfigure the FPGA depending on whether the target configuration is already loaded. In addition, what is needed is a system that allows bitstreams to be placed in a special section of the object file, allowing the linker to segregate bitstreams from other data for purposes of alignment and/or storing the bitstreams in privileged memory. In addition, what is needed is a method and apparatus for encapsulating binary machine instructions and data along with the hardware configurations required to execute the machine instructions.